At the 75th HPC User Forum in Edinburgh, Jean-Marc Denis held a keynote presentation on the European Processor Initiative. Before this, we had the chance to talk with him at large about the recent developments in the project.
Can you tell a little bit about yourself and what you do?
Jean-Marc Denis: Sure. First of all, my original position is to be at Atos where I am in charge of the technological strategy for the Big Data and Security Division. Because of my background in HPC, I have been in charge of preparing the European Processor Initiative on behalf of Atos. Then, I became Chairman of the Board for the whole project. As such, I have been invited by the HPC User Forum to deliver a keynote presentation.
What is the European Processor Initiative about?
Jean-Marc Denis: This is a project that has been launched by the European Commission. The DG Connect subbranch of the European Commission is in charge. The goal is to provide to Europe and to EuroHPC for the exascale machines that will be delivered by 2023, a European technology for the compute engines, generally speaking. It covers both the general purpose part and the accelerator part or one of the accelerator parts.
The accelerator serves to accelerate the processor?
Jean-Marc Denis: That is correct. In the industry development, we see a combination between general purpose processors and accelerators to deliver more performance. We intend to develop the two components, first the general purpose processor and secondly, one accelerator, provided that the big exascale solution will contain several flavours of accelerators.
So, it is hardware development?
Jean-Marc Denis: It is hardware development, it is silicon development. We develop one microprocessor family for general purpose processing and for acceleration. To some extent, what we plan to do, is to become through the project the European version of AMD and create a general purpose processor and an accelerator family.
AMD is a billion-euro company. We guess you do not have that kind of funds yet?
Jean-Marc Denis: Not on the short term but the ambition is really high. One of the key objectives for the European Commission is to regain full strength for the creation of the Intellectual Property (IP) as well as to get the whole value chain from the creation of the IP to the product located in Europe. That does not mean that the production has to be in Europe because there is no advanced processor manufacturer in Europe but this is a different story. In the long term, the European Commission and Europe maybe would like to regain some credibility in this area as well but in a first step, the goal is really to get control of the IP for microprocessors and accelerators back in Europe, because today, this is mostly between the United States, China, Japan and a bit of Taiwan. There is no high-end solution in Europe and we want to be back in this area.
There has been a long tradition of work on processors in Horizon 2020 research projects.
Jean-Marc Denis: That is correct. The project was born in DG Connect, as I mentioned, through the Horizon 2020 Research and Innovation Programme. As such, the goal of the European Processor Initiative (EPI) is to develop the foundations of the Intellectual Property and to transfer this to the industry. I am going to talk about that a bit later on. The industrial end of EPI will produce the microprocessor and accelerator, do the manufacturing, and sell the whole product to the original equipment manufacturers (OEM), the supercomputer designers and manufacturers like Atos in Europe, HPE/Cray, Dell, Lenovo in the United States and whoever who is interested to acquire the European technology for getting access to the European market.
It is about creating European technology. What is the connection with exascale?
Jean-Marc Denis: The goal for the project is to deliver exascale technologies. We have to deliver high-end solutions competing in the field against those of Intel, AMD, and the best-in-class Arm-based solutions. We will get very low-power consumption per performance level. The classic performance/watt issue, very high memory bandwidths, very high Flops/second, and all the features you need for high-end supercomputers, including the energy needs in artificial intelligence, and mostly in deep learning and machine learning for the training phase.
Is it all new IP? We suppose you do not start from scratch?
Jean-Marc Denis: We do not start from scratch. First of all, let us review the assets that we are building up the technology with in the hardware segment. If we want to create a complete European ecosystem from scratch, this will take very long with no short-term success in deliverables. This is something we cannot achieve. We start, at least for the general purpose processor, with existing micro-architecture and Intellectual Property. We have decided to work for the first generation with the Arm instruction set and Arm micro-architecture. We have a very close working relationship with Arm, located in the UK. It has become through time a Japanese company but all the expertise and engineers are based in the UK. While we are working with Arm for the high-end micro-architecture - and this will be the ZEUS core from Arm which is newly disclosed information - for the accelerator, we will be working with the RISC-V, which is an open source instruction set. This is compatible with the roadmap and timeline because the elementary compute element of the accelerator is very tiny. It is a very small IP, a semi-conductor segment and we can achieve that on time for the exascale machine.
Basically, we will be reusing existing IP for the general purpose processor while we will be developing our own IP, based on RISC-V, for the accelerator. Then, we will manufacture many other components like memory access, DDR5, High Bandwidth Memory (HBM), PCI Express (PCIe), or any I/O subsystem that we are building up from existing IP, because it does already exist, it is off-the-shelf from many different companies. There is no reason to reinvent the wheel in this area. So, we are going to assemble many different IPs that will be supplied from different providers.
Where are you at this point in time?
Jean-Marc Denis: We have started the developments back in December 2018. We are going to freeze quite soon the design of the general purpose processor, the main specifications, and the same for the accelerator. Then, we will start the concrete development with the ambition to tape out at the end of next year, which is very ambitious. We are using existing IP or we develop similar IP on our side, so this is really compatible and achievable with minimum risks. This is a strong ambition from that aspect. From the tape-out to the real product that we can deliver in volume, there will be again another 1,5 year. We plan to deliver the first generation of the product to the supercomputer manufacturers by the first semester, the second half of 2022.
But of course the manufacturers already know that it is coming, so they should prepare?
Jean-Marc Denis: Something very interesting in the project is based on a very successful project, also from Horizon 2020. In Horizon 2020, there were the different Mont-Blanc projects around the Arm ecosystem. In Mont-Blanc, there have been developed a lot of software components but also some hardware components. One of the very successful subprojects in Mont-Blanc was the development of a supercomputer board by Atos on which the Arm processor has been implemented. It became a standard product within the Atos product line. We plan to do exactly the same. Atos will use the processor that is designed in EPI and will develop a prototype board for the BullSequana X product line, the high-end supercomputer machines from Atos. This will be used first as a proof-of-concept funded by EPI. It will be a kind of showcase of what we can do with the European technology.
If all goes well, there could be a European exascale machine in 2023 with this technology. But the procurement for that system is also in 2022?
Jean-Marc Denis: Correct, the procurement for the exascale machines will be in 2022.
But they cannot perform benchmarking then, or can they?
Jean-Marc Denis: Not yet. Nevertheless, there will be some preliminary results because with the first prototype that will come in volume - that is something that we plan to do - we will get a first, very concrete idea of the real performances we can expect. In a way, I believe it is not a real issue if we don't deliver the best performances in the world for the general purpose processor. As I mentioned, most of the compute power will come from the accelerators. For the exascale machines, there will obviously be our own accelerator, but not only this one. There will be third-party accelerators. What is very important for the first generation of the exascale machine is the quality of the connection between the general purpose processor and the accelerator subsystem. We will have a very strong focus on the quality of the data flow in terms of latency, data processor-per-second traffic, working bandwidth, byte/flop, all the characteristics that make the flow of data between the memory and the accelerator extremely performing in terms of bandwidth, latency, and the rate. This is the key topic from this standpoint.
Obviously, we plan to deliver a very solid general purpose processor that will be able to deliver a lot of performance. For us, what is very important is not the peak performance. All of that will come in the accelerator work. What is important is the balance between the flop capacity and the memory subsystem. To this extent, we are going to put a lot of focus on the byte/flop issue. We intend to be the best in class, the best in the world with that key metric. As a consequence, the applications do not need to be fine-tuned to get performance out of the processor. Just a very good compiler like GCC or the one that is under development at Arm in the Arm ecosystem for HPC, will be good enough to obtain a lot of performance, a strong percentage of the peak, with no specific effort for the developers. This is extremely important if we want to cover a maximum number of applications, libraries, and kernels with no long rewriting, porting or optimisation at the application level.
Currently, the project is financed by the European Union Horizon 2020 Programme. Next year, there will be another funding round?
Jean-Marc Denis: That will be next year. That is part of the project as well. This is a second special Grant Agreement that will be under preparation next year to start at the implementation level by 2021.
But the amount of money they are talking about is from an order of 40 million euro?
Jean-Marc Denis: It is about 40 million euro, on top of the 80 million euro already received, that will cover all the activities for development. This is an Horizon 2020 project. This is really for covering the human cost but all the non-recoverable expanses, including all the costs associated to the tools, which are the Integrated Development Environment (IDE) tools, all the licenses from the different components, have to be supplied by different channels. This is a lot of money.
What are the novelties that you have in the architecture?
Jean-Marc Denis: This is a good question. I mentioned that we are going to build a general purpose processor based on Arm. To this extent, this is not that innovative. We are going to build up an accelerator based on RISC-V to address the needs in the high-end double precision area. This is innovative but on top of that, we are going to introduce a new concept that we call "Common Platform Concept". This is based on a combination of chiplets and interposers on which we are going to put a different IP, including the Arm and the accelerator. In addition, we are also going to introduce on that Common Platform embedded FPGA, targeting the HPC field. This means that for customers having their own specific cryptographic engines, they can select whatever subroutine or mathematical model they want to implement in FPGA. Because the FPGA is integrated in the silicon with the Arm processor, the FPGA will get full access to the memory subsystem. So, there is direct access to the Arm subsystem. There will be huge performances out-of- the-box in the FPGA area.
We are going to use as well Multi-Purpose Processing Array (MPPA), which is specific IP by Kalray. This is a company targeting the automotive market. Out of that MPPA proof-of-concept we are going to manufacture for the second revision a complete chip based on EPAC (European Accelerator based on RISC-V instruction set) and the general purpose processor, specifically addressing the needs of the automotive market in Europe. On top of that, there will be some security engines as well to protect the microprocessor from external attacks from any party. We are going to be able to guarantee to European customers that our ecosystem at silicon level is completely safe because there is no backdoor and no cryptographic risk because we control the cryptographic engine. We have the complete control of the engineering and manufacturing process. This is a big asset for the European industry and the European customers.
And this will go beyond HPC, as you said?
Jean-Marc Denis: This is a very important point. HPC is definitely the driver for the technology but we need to have a driver for the volume and to generate big business. That driver for volume will be the European car-manufacturing industry in 2024-2025 for the autonomous vehicles that will be in the streets by that time. This is why we have in the EPI consortium German companies like BMW, Infineon, and Elektrobit which are amongst the top of companies for developing the most advanced technologies for autonomous vehicles. Specifically for BMW, it is very interesting because they could have a European alternative source for their electronic components that will be in their autonomous cars. They will have a footprint inside the development cycle of the IP for the European microprocessor and accelerator which is very important for them and for European car manufacturers as it helps to make their mind up about their strategy.
This would give them an edge towards foreign car-manufacturing companies. Thank you very much for this interview.